Digital VLSI for Neural Networks

Priyanjali Jain¹ , Priyanshu Jain²

Section:Survey Paper, Product Type: Journal-Paper
Vol.7 , Issue.4 , pp.47-52, Dec-2020

Online published on Dec 31, 2020

Copyright © Priyanjali Jain, Priyanshu Jain . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
 

View this paper at   Google Scholar | DPI Digital Library

XML View     PDF Download

How to Cite this Paper

Abstract :
This chapter discusses digital electronic implementations of ANNs. First, we look at the differences between digital and analog design techniques with a focus on cost- performance trade-offs. Second, we consider the use of traditional processors in parallel configurations for ANN emulation. Third, to convey a sense of some of the issues involved in designing digital structures for ANN emulation, a custom digital ANN processor is discussed: the Adaptive Solutions CNAPS. Although this chip is no longer produced, it is still being used. It’s simple architecture makes it a good vehicle to understand the trade-offs inherent in emulating neural structures digitally. And fourth, we look briefly at FPGA technology as a promising alternative for digital implementation of ANNs.

Key-Words / Index Term :
ANN , CNAPS, FPGA

References :
[1] Ambros-Ingerson, J., R. Granger, et al., 1990, Simulation of Paleocortex Performs Hierarchical Clustering, in Science 247, pp.1344-1348.
[2] Bailey, J., 1993, A VLSI Interconnect Strategy for Biologically Inspired Artificial Neural Networks, PhD Thesis, Department of Computer Science / Engineering, Beaverton, OR, Oregon Graduate Institute.
[3] Bailey, J. and D. Hammerstrom, 1988, Why VLSI Implementations of Associative VLCNs Require Connection Multiplexing, 1988 International Conference on Neural Networks, pp.173-180.
[4] Boahen, K. A., 2000, Point-to-Point Connectivity Between Neuromorphic Chips Using Address Events, IEEE Transactions on Circuits and Systems II - Analog and Digital Signal Processing , 47(5), pp.416-434.
[5] Braitenberg, V. and A. Schüz, 1998, Cortex: Statistics and Geometry of Neuronal Connectivity , Springer-Verlag.
[6] Chua, L. and T. Roska, 2001, Cellular Neural Networks and Visual Computing , Cambridge University Press.
[7] Fahlman, S. E. and M. Hoehfeld, 1992, Learning with Limited Numerical Precision Using the Cascade-Correlation Algorithm, IEEE Transactions on Neural Networks , 3(4), pp. 602-611.
[8] Hammerstrom, D., 1995, A Digital VLSI Architecture for Real-World Applications, An Introduction to Neural and Electronic Networks , S. F. Zornetzer, J. L. Davis, C. Lau and T. McKenna, San Diego, CA, Academic Press, pp.335-358.
[9] Hatano, F. and et al., 1999, Implementation of Cell Array Neuro-Processor by Using FPGA, International Joint Conference on Artificial Neural Networks, Washington DC, IEEE.
[10] Hennessy, J. L. and D. A. Patterson, 1991, Computer Architecture: A Quantitative Approach , Palo Alto, CA, Morgan Kaufmann.
[11] Intel, 2001, IA-32 Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture, Intel, 2001.
[12] Reschke, C., T. Sterling, et al., 1996, A Design Study of Alternative Network Topologies for the Beowulf Parallel Workstation , High Performance and Distributed Computing.
[13] Shan, H., J. P. Singh, et al., 2000, A Comparison of Three Programming Models for Adaptive Applications on the Origin2000 , Proceedings of SC2000, Dallas, TX.
[14] Sharma, A. K., 1998, Programmable Logic Handbook - PLDs, CPLDs & FPGAs , McGraw-Hill Handbooks.